• Energy Research

In this paper, we study a compiler-based approach to reducing the instruction SPM leakage energy efficiently, which can also minimize the performance overhead. Our evaluation indicates that the compiler-based approach is superior to periodical or bank-based methods. On average, the compiler-based method can reduce the SPM leakage energy by nearly 89.82%, with only 0.25% performance overhead.

In this paper, we present two methods to reduce leakage energy by dynamically resizing the cache during program execution. The first method monitors the miss rate of the individual subbanks (in a subbanked cache structure) and selectively shuts them if their miss rate falls below a predetermined threshold. Simulations on SPECJVM98 benchmarks show that for a 64K I-cache, this method results in a leakage reduction of 17-69% for a 4 subbank structure and 20-75% for a 8 subbank structure when the performance penalty is <1%. The second method dynamically resizes the cache based on whether the macro-blocks (a group of adjacent cache blocks) are being heavily accessed or not. This method has higher area overhead but greater leakage energy reduction. Simulations on the same set of benchmarks show that this method results in a leakage reduction of 22-81% for the I-cache when the performance penalty is <0.1%, and 17-85% for the D-cache when the performance penalty is <1%.

It has been shown previously that blended simultaneoussource data can be successfully separated using an iterative seislet thresholding algorithm. I combine the iterative seislet thresholding with the recently proposed local signal-and-noise orthogonalization via the shaping regularization framework. During the initial iterations, the deblended data and its blending noise section are not orthogonal to each other, indicating that the noise section contains significant coherent useful energy. Although the leakage of useful energy can be retrieved by updating the deblended data from the data misfit during many iterations, I propose to accelerate the retrieval of the leakage energy using iterative orthogonalziation. Simulated synthetic and field data examples show superior performance of the proposed approach.

Scratch-Pad Memories (SPMs) have been increasingly used in embedded systems, for which it is important to reduce the leakage energy consumption. While there are several techniques to reduce the leakage energy for cache memories, those techniques may result in significant performance overheads for instruction SPMs. In this paper, we study a compiler-based approach to reducing the instruction SPM leakage energy efficiently, which can also minimize the performance overhead. Our evaluation indicates that the compiler-based approach is superior to periodical or bank-based methods, all of which use drowsy techniques. On average, the compiler-based method can reduce the SPM leakage energy by nearly 89.82%, with only 0.25% performance overhead.

We present an accurate model of the self-heating effect in the Spin-Torque-Transfer RAM (STTRAM) using finite-volume-methods and thermal RC based compact models. We couple device level thermal simulation to the self-heating phenomenon to show that self-heating during write operation can result in significant temperature increase in STTRAM which in turn adversely affect the read disturb, leakage energy and sensing accuracy.

The Improved DFT-based Channel Estimation Algorithm for MIMO-OFDM System uses the symmetric property to extend the LS estimate in frequency domain, and calculates the changing rate of the leakage energy, and selects useful paths by the changing rate.

As process technology advances toward deep submicron (below 90 nm), static power becomes a new challenge to address for energy-efficient high performance processors, especially for large on-chip array structures such as caches and prediction tables. Value prediction appeared as an effective way of increasing processor performance by overcoming data dependences, but at the risk of becoming a thermal hot spot due to the additional power dissipation. This paper proposes the design of low-leakage value predictors by applying static decay techniques in order to disable unused entries from the prediction tables. We explore decay strategies suited for the three most common Value predictors (STP, FCM and DFCM) studying the particular tradeoffs for these prediction structures. Our mechanism reduces VP leakage energy efficiently without compromising VP accuracy nor processor performance. Results show average leakage energy reductions of 52%, 65% and 75% for the STP, DFCM and FCM value predictors, respectively.

“Coupled inductor and voltage doubler based boost converter for high step-up application.” is introduced. The presented converter is employed with coupled inductor and voltage extension cell. The proposed converter provides high conversion ratio, less stresses across active switch and tremendous utilization of leakage energy. The operational principle and steady state analysis is expressed within this article 20V/400V, 200W converter is developed in MATLAB simulink.